I. Field of the Invention
The present invention relates generally to systems which utilize memory array architectures. More specifically, the invention relates to a system and method for an improved sense amplifier architecture.
II. Description of the Related Art
Electronic systems typically store data during operation in a memory device. Dynamic random access memory (DRAM) is very popular as a data storage device for such systems. Basically, a DRAM is an integrated circuit that stores data in binary form (e.g., “1” or “0”) in a large number of cells. The data is stored in a cell as a charge on a capacitor located within the cell. Typically, a high logic level is approximately equal to the power supply voltage and a low logic level is approximately equal to ground.
The cells of a conventional DRAM are arranged in an array so that individual cells can be addressed and accessed. The array can be thought of as rows and columns of cells. Each row includes a word line that interconnects cells on the row with a common control signal. Similarly, each column includes a digit line that is coupled to at most one cell in each row. Thus, the word and digit lines can be controlled so as to individually access each cell of the array.
To read data out of a cell, the capacitor of a cell is accessed by selecting the word line associated with the cell. A complementary digit line that is paired with the digit line for the selected cell is equilibrated to an equilibrium voltage. This equilibration voltage (Veq) is typically midway between the high Vcc and low Vss (typically ground) logic levels. Thus, conventionally, the digit lines are equilibrated to one-half of the power supply voltage, VCC/2. When the word line is activated for the selected cell, the capacitor of the selected cell discharges the stored voltage onto the digit line, thus changing the voltage on the digit line.
Referring to FIG. 1, a sense amplifier 110 detects and amplifies the difference in voltage on the pair of digit lines. The sense amplifier 110 typically includes two main components: an n-sense amplifier and a p-sense amplifier. As illustrated in FIG. 1, the n-sense amplifier includes a cross-coupled pair of n-channel transistors 230, 232, in which the gates of the transistors 230, 232 may be coupled to the digit lines 102 and 104 or 106 and 108. Thus, during a read operation, the n-channel transistors 230, 232 are initially driven by the equilibration voltage on the digit lines 102 and 104 or 106 and 108. The n-sense amplifier is used to drive a low digit line to ground. The p-sense amplifier includes a cross-coupled pair of p-channel transistors 234, 236 and is used to drive a high digit line to the power supply voltage.
An input/output device for the array, typically an n-channel transistor 240, 242, passes the voltage on the digit line 102, 104 or 106, 108 for the selected cell to an input/output line 244, 246 for communication to, for example, a processor of a computer or other electronic system associated with the DRAM. In a write operation, data is passed from the input/output lines 244, 246 to the digit lines 102, 104, 106, 108 by the input/output device 240, 242 of the array for storage on the capacitor in the selected cell.
Each of the components of a memory device are conventionally formed as part of an integrated circuit. To more effectively use the area of the integrated circuit, the memory array may include sub-arrays which may have sense amplifier circuitry shared amongst the sub arrays. In such memory devices, the sub-arrays are coupled to the sense amplifier 110 through isolation transistors 202, 204, 206, 208, typically n-channel transistors. The n-channel isolation transistors 202, 204, 206, 208, selectively couple the sense amplifier 110 to the digit lines 106 and 108 or 102 and 104 for a data reading or writing operation, as is well known in the art.
The above arrangement of shared sense amplifiers is illustrated on a higher level in FIG. 2 and is commonly referred to as an interleaved folded scheme. In this scheme digit pairs (e.g., two digit lines) are interleaved and run next to each other inside a sub-array 112, 114. Each digit pair forms a true and complement combination which is read by and written to by a sense amplifier 110. Each of the digits lines, e.g. 102, of a pair, e.g. 102, 104, is coupled to a memory cell of a sub-array, each cell including a capacitor connected through an access transistor to the digit line. Referring to FIGS. 1 and 2, the digit pair 102, 104 is connected to a sense amplifier 110 by a pair of isolation transistors 206, 208. Also, sharing the same selected amplifier 110 is another digit pair 106, 108 from another sub-array 114. Digit pair 106, 108 is isolated from the sense amplifier 110 by isolation transistors 202, 204 during sensing of digit pair 102, 104. As shown in FIG. 1, this isolation occurs, for example, by turning off a pair of isolation transistors 202, 204 between the sense amplifier 110 and digit pair 106, 108. The interleaved folded scheme requires that one sense amplifier fit in the space of 4 digit lines of the adjacent arrays. The interleaved folded digit line scheme works well with 8F**2 type memory cells, which are commonly used with such a scheme. The name, 8F**2, is descriptive of the area each memory cell occupies in terms of the industry standard “F units.”
Another known memory cell arrangement is known as 6F**2 cells. The 6F**2 cells are different from the 8F**2 cells in that for an interleaved folded scheme a sense amplifier 110 must fit into the width of two (2) digit lines rather than within the space of four (4) digit lines as are used with 8F**2 cells. While 6F**2 memory cells can be utilized with the same sense amplifier layout shown in FIG. 1, this may require extremely tight design rules or additional interconnects. Therefore, there exists a need for a more efficient sense amplifier scheme layout which is better suited for 6F**2 memory cells.